The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of the IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, as the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design have resulted in the development of multilayer integrated devices such as field effect transistor (FET). The FET device may include interlayer dielectric layers (ILD) having interconnects aligned with underlying layers. However, as the scaling down continues, aligning the interconnects of the ILD layers has proved difficult. Although existing FET devices and methods of fabricating FET devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.